The present invention relates to a semiconductor memory device of double-data rate (DDR) mode, and more particularly an output control circuit for use in semiconductor memory devices of double-date rate mode.
In synchronous semiconductor memory devices hitherto developed, the timing of outputting data is controlled by the clock signal . The output control circuit of each semiconductor memory device therefore has an output register.
FIG. 1 shows a conventional output register R10, and FIG. 2 is a timing chart explaining the operation of the output register. As shown in FIG. 1 the output register R10 comprises a master latch M10 and a slave latch S10. The master latch M10 is composed of clocked inverters C11 and C12 and an inverter I11. Clock signals CKM and CKM (i.e., signal obtained by inverting the signal CKM) are input t o the clocked inverters C11 and C12, respectively. The slave latch S10 is composed of clocked inverters C13 and C14 and an inverter I12. Clock signals CKS and CKS (i.e., signal obtained by inverting the signal CKS) are in put to the clocked inverters C13 and C14, respectively.
How the output register R10 operates will be described. The master latch M10 and the slave latch S10 can assume two operating states each. The first is through state, in which the input data is transferred to the output. The second is latch state, in which the input data is held, or latched. A clock signal CKM is supplied to the master latch M10 to control the state thereof. Similarly, a clock signal CKS is supplied to the slave latch S10 to control the state thereof. The clock signals CKM and CKS are input in opposite phases. Hence, the master latch M10 and the slave latch S10 assumes opposite states. That is, the latches M10 and S10 assume the latch state and the through state, respectively, or other way around.
The operation of the output register R10 will be explained in greater detail. When the clock signal s CKM and CKS are at "H" level and "L" level, respectively, the master latch M10 is in the latch state, whereas the slave latch S10 is in the through state. The states of the master latch M10 and slave latch S10 change to the through state and the latch state, respectively, when the clock signal CKS is set at "H" level, changing the state of the slave latch S10 to the latch state at time tB (FIG. 2), and the lock signal CKM is set at "L" level, changing the state of the master latch M10 to the through state at time tC (FIG. 2). As seen from FIG. 2, the time tC (FIG. 2) is slightly behind the time tB.
Thus, at time tB, the slave latch S10 starts holding input data D1 the master latch M10 latched and started holding at time tA, the start of the cycle of the clock signal CKM. The master latch M10 transfers the input data D1 at time tC, and latches data D2 at time tA'. The output of the slave latch S10, which is the output of the output register R10, is the data that was input to the output register R10 at the beginning of each cycle of the clock signal CKM.
The data output from the output register R10 is transferred to an external output circuit in most cases. In order to minimize the delay of signals, the output register R10 is provided near an output pad.
In a multi-bit semiconductor memory device, output registers are arranged in the device chip, greatly spaced from one another, each together with one output pad. Clock signals are supplied from the clock signal generating circuit to the output registers, each for controlling one output register. Since the output registers are greatly spaced, the clock signal line is very long and has high parasitic resistance. Not only the capacitance of the load that should be driven by the lock signal, but also the capacitance of the clock signal line increases inevitably. Namely, the RC delay of the clock signal is increases. This impairs the performance of the multi-bit semiconductor memory device. To make matters worse, the RC delay of the clock signal in each output register differs from that in any other output register, depending on the position of the output register. Consequently, the output registers vary in their output data, giving rise to problem called "clock skew".
Generally, in order to reduce the RC delay, a global clock signal is input to a local clock buffer. To prevent clock skew, the clock signal line is arranged so that the RC delay of the clock signal may have the same value in every output register. Whatever measures are taken to reduce the RC delay and prevent clock skew, it would be important to minimize the capacitance of the load that should be driven by the clock signal.
An output control circuit of DDR mode that incorporates output registers of the type shown in FIG. 1 will be described with reference to FIG. 3.
In synchronous semiconductor memory devices of single-data rate (SDR) mode, data is latched at each leading edge of the clock signal, or at the start of the cycle of the clock signal for controlling the output data. In synchronous semiconductor memory devices of DDR mode, data is latched not only at each leading edge of the clock signal, but also at each trailing edge thereof, i.e., the middle of the cycle of the clock signal.
In a semiconductor memory device of DDR mode, only one address data is usually input. The data designated by the address data and the data generated in the memory device will be output from the memory device. In the DDR-mode memory device, twice as much data is transferred within a unit time as in an SDR-mode memory device. It takes almost the same time to read data from a memory cell in the DDR-mode memory device as in the SDR-mode memory device. Thus, in the DDR-mode memory device, the memory cell designated by the input address and the memory cell designated by the address generated in burst mode are selected at the same time. Hence, the data items stored in these cells are detected simultaneously.
In the output control circuit of DDR mode, shown in FIG. 3, such two data items are supplied through two data lines DL1 and DL2 to the output registers R11 and R12. Subsequently, the data items are held in the output registers R11 and R12, respectively.
As shown in FIG. 3, the output registers R11 and R12 are connected at output to a multiplexer 40. As can be understood from FIG. 4, the multiplexer 40 outputs the data held in the first output register R11 to an external output circuit 42 during the first half of the cycle of the clock signal, and outputs the data held in the second output register R12 to the external output circuit 42 during the second half of the cycle of the clock signal. The data thus held in the external output circuit 42 is output when it is required.
The relation between the address of the data output from the register R11 during the first half of the cycle and the address of the data output from the register R12 during the second half of the cycle depends upon whether the burst mode is a linear one or an interleaved one. If the burst mode is an interleaved one, the relation between the addresses is altered or switched in accordance with a start address. Therefore, each of two data items simultaneously read from two memory cells must be stored into either the output register R11 or the output register R12, in accordance with the relation between the addresses. To this end, a bus exchanger 44 is connected to the inputs of the output registers R11 and R12. The bus exchanger 44 controls the connection of the data buses which are provided between the memory cells, on the one hand, and the output registers R11 and R12, on the other. More precisely, the bus exchanger 44 connects one cell to the output register R11 or the output register R12, in accordance with preset conditions. The bus exchanger 44 may be of the type disclosed in Japanese Patent Application No. 9-295431.
In a DDR-mode semiconductor memory device, the output registers are connected in parallel as is shown in FIG. 3. Thus, the DDR-mode memory device needs to have twice as many output registers as the SDR-mode memory device. Hence, the gate capacitance of the load that should be driven by a clock signal (CKM or CKS shown in FIG. 3) for controlling one output register is twice as much. The problems inherent in the SDR-mode memory device, i.e., clock skew and low performance resulting from RC delay of the clock signal, are more acute in the DDR-mode memory device. As a consequence, data cannot be reliably read from the DDR-mode memory device at twice as high a frequency as from the SDRmode memory device.